The invention relates to a process for timing recovery in which the phase of an input clock pulse is compared with that of an output clock pulse, and in which the frequency of the output clock pulse is readjusted as a function of the result of comparison with the aid of a correcting quantity, and to a device for carrying out this process.
Such a process is known from the book "Theorie und Anwendungen des Phase-locked Loops", Best, 4th revised edition, AT Verlag Aarau, Stuttgart, 1987, pages 93 to 95.
A timing recovery device having a phase-locked loop, in which there is derived from the frequency of a quartz oscillator a sequence of phase-shifted internal clock pulses of which in each case one serves, controlled by the output signals of a phase discriminator, as readout pulse after frequency division, is the subject of U.S. Pat. No. 5,017,801.
A changeover is presently taking place in the technology of the transmission and multiplexing of digital signals from a plesiochronous to a synchronous operation. Whereas the conventional plesiochronous signals have a bit structure, the new synchronous signals have a byte structure, that is to say are organized in multiples of eight bits. This emerges from the CCITT Recommendations G.707, G.708 and G.709.
In multiplex technology, a plurality of digital signals are combined by interleaving to form a time-division multiplex signal. In the synchronous digital multiplex hierarchy this takes place in accordance with the byte structure in groups of respectively eight bits. Since the phases of the digital signals to be interleaved are frequently not fixed relative to one another, but drift with respect to one another as a function of the prehistory, it is necessary during interleaving to connect upstream phase matching.
The phase matching is performed by stuffing. In this case, in prescribed discrete time positions (time slots) of the outgoing multiplex signal either eight time slots assigned to the signal to be multiplexed are filled with its data or not--as a function of the instantaneous phase or frequency of the signal to be multiplexed relative to the multiplex signal. During stuffing, the phase of the synchronous signal to be multiplexed jumps accordingly by eight UI (unit intervals), or by one byte (8 bits), relative to the multiplex signal.
After transmission, the multiplex signal is once again resolved into its individual components. One of the problems thereby arising is the recovery of the original clock pulses of the multiplexed signals, for high demands are placed on the uniformity of these recovered clock pulses.
Irregularities occurring in the temporal sequence of the clock pulse edges are referred to as jitter. Since the jitter generated in different transmission links add together in their series connection, the jitter occasioned by individual causes must be narrowly limited. This also applies to the jitter that is caused by stuffing-induced phase-jumps.
A peculiarity of the transmission of digital signals resides in that phase fluctuations proceeding very slowly, so-called drift, are effectively tolerated by the transmission devices. Its permissible limiting values are therefore substantially higher than those of jitter.